LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY addr_mux IS
	PORT(
		control:			IN		STD_LOGIC_VECTOR (1 downto 0);
		status:				IN		STD_LOGIC_VECTOR (1 downto 0);
		direct_addr_in:		IN		STD_LOGIC_VECTOR (6 downto 0);
		clk:				IN		STD_LOGIC;
		
		address_out : 		OUT 	STD_LOGIC_VECTOR (8 downto 0)
	);
END;

ARCHITECTURE behaviour OF addr_mux IS

signal address : 		STD_LOGIC_VECTOR (8 downto 0);
signal reg_bank : 		STD_LOGIC_VECTOR (1 downto 0);
signal direct_addr:		STD_LOGIC_VECTOR (6 downto 0);

BEGIN
	reg_bank <= status(1 downto 0);
	direct_addr <= direct_addr_in;
	
	process(direct_addr, control)					
	begin
		case control is
			when B"00" =>						--direct address
				address(8 downto 7) <= reg_bank;
				address(6 downto 0) <= direct_addr;
			when B"01" =>
				address <= B"000000010";		--PCL
			when B"10" =>
				address <= B"000001010";		--PCLATH
			when B"11" =>
			when others =>
		end case;
	end process;	
	
	address_out <= address;
END;








